Voltage controlled oscillator runaway prevention

摘要

A feedback module for preventing voltage controlled oscillator (VCO) runaway in a phase locked loop (PLL) circuit can include a first, a second, and a third input to receive a first output signal from a PLL circuit, a reference signal, and a first control signal. The feedback module may also include a feedback circuit to generate a second control signal, the second control signal being coupled to an input of the PLL circuit, wherein the feedback circuit generates the second control signal by comparing a number of cycles of the first output signal to a first threshold, and a number of cycles of the reference signal to a second threshold.

主权项

1. A circuit for preventing voltage controlled oscillator (VCO) runaway in a phase locked loop (PLL) circuit, the circuit comprising:
a PLL circuit, the PLL circuit including:
a phase detector circuit having a reference input, a feedback input, a first control input, and increment and decrement outputs, the reference input coupled to a reference clock signal;a charge pump circuit having an increment input, a decrement input, and a charge pump output, the increment and decrement inputs respectively coupled to the increment and decrement outputs of the phase detector circuit;a filter circuit having a filter input and a filter output, the filter input coupled to the charge pump output;a voltage controlled oscillator (VCO) circuit having a VCO input, and a VCO output, the VCO input coupled to the filter output;a feedback divider circuit having a feedback divider input and a feedback divider output, the feedback divider input coupled to the VCO output, the feedback divider output coupled to the feedback input; and a feedback circuit, the feedback circuit including:
a first frequency divider, the first frequency divider having a first enable output, a second control input, a first enable input and a first clock input, the second control input coupled to a control signal, the first clock input coupled to the VCO output;a second frequency divider, the second frequency divider having a second enable output, a third control input, second and third enable inputs, and a second clock input, the third control input coupled to the control signal, the second enable input coupled to the first enable output, the second clock input coupled to the reference clock signal;a first inverter, the first inverter having a first inverter input coupled to the first enable output and a first inverter output coupled to the first enable input,a second inverter, the second inverter having a second inverter input coupled to the second enable output and a second inverter output coupled to the third enable input;an AND logic gate, the AND logic gate having first and second logic inputs and a first logic output, the first logic input coupled to the control signal, the second logic input coupled to the first inverter output;an OR logic gate, the OR logic gate having third and fourth logic inputs and a second logic output, the third logic input coupled to the first logic output, the fourth logic input coupled to the second enable output, the second logic output coupled to the first control input;wherein the first frequency divider generates the first enable output by comparing a number of cycles of the VCO output to a first threshold, and the second frequency divider generates the second enable output by comparing a number of cycles of the reference clock signal to a second threshold.