| 摘要 |
<p>An addressable signalling apparatus wherein a shift register may be sequentially advanced through units of address by inputs to an OR gate. Such inputs may come from programmable connectors connected to selected input terminals defining a unique address or from one designated connector which is connected as an input to each of said OR gates defining an address unit substitute. The OR gates are connected in turn to a shift register which, when it sequentially shifts through programmed units of address, activates an output means. Once the output is enabled, a multiplicity of output messages may be transmitted through the apparatus. The apparatus includes a logic circuit for resetting the shift means in the event an input not corresponding either to the programmed units of address or the common designated substitute address unit is received.</p> |
