| 摘要 |
A circuit arrangement for reshaping a pulse edge data signal whose pulse edges signal binary values of data into an amplitude data signal whose amplitudes signal the binary values of the data includes a pulse generator to produce a timing signal having a period duration which is equal to the duration of the individual binary values. A pulse shaper is fed with the pulse edge data signal and emits a rectangular signal whose rectangular pulses are of short duration and coincide with the pulse edges of the pulse edge data signal. A first bistable trigger stage and a second bistable trigger stage are provided, each of which has a setting input, a data input, a pulse train input and an output, the output emitting signals having binary values which signal the stable states of the two trigger stages. The setting input of the first trigger stage is supplied with the rectangular signal and the pulse train input of the first trigger stage is fed with a timing signal. The first trigger stage assumes one of its two stable states when a rectangular pulse of the rectangular signal occurs and assumes the other of its two stable states when, in the absence of the rectangular pulses, a pulse edge of the timing signal is present at the pulse train input of the first trigger stage. The output of the first trigger stage is connected to the data input of the second trigger stage and the timing signal is fed to the pulse train input of the second trigger stage. The second trigger stage assumes the states of the first trigger stage when one of the edges of the timing signal occurs, and the amplitude data signal is emitted by way of the output of the second trigger stage. |
