发明名称 HIGH SPEED FRAME SYNCHRONIZATION ESTABLISHMENT DEVICE
摘要 PURPOSE:To establish frame synchronization at a high speed without errors by dividing a one period frame into plural small synchronous frames and adding controls information in a device which synchronizes frames which have been time division-multiplexed. CONSTITUTION:In an asynchronous state, reception/transmission frame switching parts 12 and 25 are switched to the side of small frame detection/generation circuits 15 and 22. At that time, the circuit 22 transmits a synchronous small frame (SFA)23 in which synchronous information S is set to be synchronous. When the side of an opposite device receives SFA, it transmits a synchronous small frame(SFS) 16 in which information S is set to be synchronous. When the circuit 15 receives SFS16, the switching part 25 transmits an information frame 27 from an information frame generation circuit 26 through the circuit 22, and one frame is synchronized. The circuit 15 is switched to an information frame detection circuit 19 and it receives an information frame 18. The circuit 19 executes monitor by a synchronous bit F, and repeats a processing similar to the asynchronous state when a step-out occurs. Consequently, synchronization is attained at the high speed without the errors in a small frame unit.
申请公布号 JPH01305738(A) 申请公布日期 1989.12.11
申请号 JP19880135810 申请日期 1988.06.03
申请人 NEC CORP 发明人 MATSUSHITA HIDEAKI
分类号 H04J3/06;H04L7/08 主分类号 H04J3/06
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