| 摘要 |
PURPOSE:To reduce the working load of a processor and at the same time to ensure stable and assured output control to a memory, by using an output circuit which transmits successively the data given from an input/output memory to the outside and an output control circuit. CONSTITUTION:For transfer of data, the parallel data given from a processor CPU are supplied successively to an input/output circuit FIFO and stored once there. Then these parallel data are converted into serial data via an output circuit OC and transmitted in the form of the output data D0. In this case, an output control circuit OCT transmits a read start signal SO and an action start signal STR' in accordance with the coincidence obtained between the conditions where a transmission preparation end signal OR and those where an inactive signal BUSY' is given. As a result, the output control of the memory regardless of the processor. This circuit reduces the working load of the processor and also ensures the stable and assured control to the memory. |
