发明名称 |
OVERLAPPED SIGNAL TRANSITION COUNTER |
摘要 |
<p>OVERLAPPED SIGNAL TRANSITION COUNTER A counter circuit counts all transitions of two or more overlapped out of phase bi-level signals under control of a start signal by combining the input signals via an exclusive OR circuit into a single signal having the transitions of all input signals. The levels of this single signal are applied to a polarity hold circuit and the level present upon the occurrence of an asynchronously occurring start signal is stored therein. The polarity hold circuit provides a pair of gating signals to a logical AND/OR network having an output containing both the positive and negative transitions of the single signal. The detected transitions are fed into a binary counter whose first stage consists of the AND/OR network.</p> |
申请公布号 |
CA1047607(A) |
申请公布日期 |
1979.01.30 |
申请号 |
CA19750237282 |
申请日期 |
1975.10.08 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CHECK, GLENN P.;DIMMICK, ROGER F. |
分类号 |
G05D3/12;G06K15/16;H03K21/02;H03K21/40;(IPC1-7):03K21/06 |
主分类号 |
G05D3/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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