发明名称 |
Signal line impedance verification tool |
摘要 |
A computer-implemented method for verifying impedance of a signal line in an electrical circuit layout includes reading a desired impedance value for a signal line and identifying the signal line in a circuit design database. A window is established around the signal line in which circuit elements will be included in an impedance calculation for the signal line. The impedance of the signal line is calculated based on the circuit elements inside the window. The signal line is flagged if the calculated impedance differs from the desired impedance value.
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申请公布号 |
US6859915(B1) |
申请公布日期 |
2005.02.22 |
申请号 |
US20030365848 |
申请日期 |
2003.02.13 |
申请人 |
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. |
发明人 |
FRANK MARK D.;NELSON JERIMY C.;BOIS KARL J. |
分类号 |
G06F17/50;H05K1/02;H05K3/00;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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