| 发明名称 |
CLOCK DRIVER CIRCUIT |
| 摘要 |
PURPOSE:To secure a coincidence between the delay time and the rise and fall time when the switching element is driven, by using both the inverse and non-inverse output of the input clock signal as a complementary clock signal each. |
| 申请公布号 |
JPS53139456(A) |
申请公布日期 |
1978.12.05 |
| 申请号 |
JP19770054151 |
申请日期 |
1977.05.11 |
| 申请人 |
NIPPON ELECTRIC CO;NIPPON TELEGRAPH & TELEPHONE |
发明人 |
KATOU GIICHI;OOWADA NORIHIKO;KIMURA TADAKATSU |
| 分类号 |
G11C19/00;G06F1/06;G06F1/10;H03K3/02;H03K5/15;H03K5/151;H03K19/00;H03K19/0175;H03K19/096 |
主分类号 |
G11C19/00 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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