发明名称 |
Clock driven voltage comparator employing master-slave configuration |
摘要 |
A pair of clock driven voltage comparators are arranged in a master-slave configuration so that voltage comparisons are made only on a clock edge and the output is held valid over the entire clock period. Each comparator stage includes a latch to lock the comparator output in the logical state it was in when the latch was enabled.
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申请公布号 |
US4121120(A) |
申请公布日期 |
1978.10.17 |
申请号 |
US19770793980 |
申请日期 |
1977.05.05 |
申请人 |
TEKTRONIX, INC. |
发明人 |
WETTERLING, STEVEN E. |
分类号 |
G01R19/165;H03K3/023;H03K3/0233;H03K3/2885;H03K5/08;(IPC1-7):G11C7/06 |
主分类号 |
G01R19/165 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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