发明名称 |
ADDITION*SUBTRACTION SYSTEM FOR PLURAL INPUT DATA |
摘要 |
PURPOSE:To ensure a high-speed process with reduced number of IC, by applying the carry generated from the unit circuit, except for the gathering of the unit circuits which obtain the final output, ti the next-step unit circuit in the form of the higher rank bit of the unit circuit output. |
申请公布号 |
JPS53112626(A) |
申请公布日期 |
1978.10.02 |
申请号 |
JP19770027787 |
申请日期 |
1977.03.14 |
申请人 |
TOKYO SHIBAURA ELECTRIC CO |
发明人 |
KITAMURA SHIYUNJI;SAKAUCHI AKIRA |
分类号 |
G06F7/509;G06F7/50;G06F7/506;G06F7/508 |
主分类号 |
G06F7/509 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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