| 摘要 |
1501351 Selective signalling WESTINGHOUSE ELECTRIC CORP 13 Jan 1976 [7 Feb 1975] 1231/76 Heading G4H [Also in Division H2] So long as conditions at the far end of a polyphase line are normal, a reference signal comprising a particular sequence of bits is sent repetitively to the near end via a single transmission link, but when a fault is sensed the reference signal is suppressed and instead signals representing operating conditions at the far end are transmitted using time-division multiplex techniques. At the near end, reception of the reference signal is used to inhibit the T.D.M. decoder but at the same time keep it synchronized with the coder at the other end. As soon as the receiver recognizes that the reference signal is no longer being received, however, the decoder is rendered operative and a blocking signal is removed from a protective system. The transmitter/coder at the far end (Fig. 3) comprises a counter 148 driven by a clock 144 to provide signals on each of its six outputs in sequence. Under normal conditions these outputs enable AND gates 124-129 to turn to that reference sequence of bits 111000 is repetitively transmitted via gates 131, 139. Under fault conditions, however, gate 120 provides an output which inhibits the AND gates 124-129 and instead removes blocking signals from three further AND gates 133-135. The counter 148 now enables these three gates in sequence so that measuring signals on lines 28-30 are time division multiplexed and transmitted. The receiver/decoder (Fig. 4) comprises a shift register 160 coupled to a set of six gates 178-183 which together recognize whether what is in the shift register is the reference sequence 111000 or a "shifted" version thereof. The decoder proper comprises a counter 176 driven by a synchronized receiver clock 166 and enabling decoding gates 162-164 in sequence. So long as the reference sequence is being received the output of gate 186 blocks the decoding gates, but a counter 189 resynchronizes the decoding counter 176 at regular intervals, being itself resynchronized by a further counter 174. When the reference sequence is not being received the decoding gates 162-164 are enabled and provide demultiplexed outputs via flip-flops 196-198. |
