发明名称 INPUT*OUTPUT SYSTEM
摘要 An input/output system includes at least a pair of processing units and system interface apparatus for comparing the results produced by both halves of the pair during normal system operation under control of a main or host processing unit. The system interface apparatus includes comparison circuits for detecting a mis-compare between the results of each half and sequence control logic circuits which are conditioned upon the occurrence of a mis-compare to unlock or deconfigure the pair to establish in a predetermined manner which of the processing units is faulty. The system interface apparatus, following signal indications of a certain minimum confidence within a processing unit, continues testing of the processor using stored diagnostic routines to determine which one of the processing units is good. It then stops the operation of the bad processing unit and enables system operation to be continued with the good processing unit. To ensure reliable processing, both halves of the pair are tested when a miscompare cannot be related to an error condition associated with one of the pair notwithstanding the fact that the first processing unit tests well. Following reconfiguration, the operating system associated with the system provides periodic testing of the good processing unit, thereby ensuring that the system continues to operate reliably.
申请公布号 JPS5391542(A) 申请公布日期 1978.08.11
申请号 JP19770137229 申请日期 1977.11.15
申请人 HONEYWELL INF SYSTEMS 发明人 JIYON EMU UTSUZU;MARION JII POOTAA;DONARUDO BUI MIRUSU;EDOWAADO EFU UERAA ZA SAADO;GAABIN UESUREE PATAASON;AANESUTO EMU MONAHAN
分类号 G06F11/18;G06F11/07;G06F11/16;G06F11/20;G06F11/22;G06F13/00 主分类号 G06F11/18
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