发明名称 DIGITAL PULSE DOUBLER HAVING 50* DUTY CYCLE
摘要 A symmetrical duty cycle waveform at twice the input frequency is provided for use as in a programmable tone generator by a quad two-input integrated circuit device using two RC delay circuits. By varying the delay circuits, two separate clock pulses with different duty cycles can be provided at the original clock frequency.
申请公布号 JPS5371556(A) 申请公布日期 1978.06.26
申请号 JP19770134520 申请日期 1977.11.09
申请人 MOTOROLA INC 发明人 DONARUDO KIYARORU RAION
分类号 G10H5/00;H03K5/00 主分类号 G10H5/00
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