| 发明名称 |
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE |
| 摘要 |
PURPOSE:To form P-type channel layers of a P-channel depletion mode MOS transistor and N-channel enhancement mode MOS transistor simultaneously by using a semiconductor layer formed on a sapphire substrate. |
| 申请公布号 |
JPS5371586(A) |
申请公布日期 |
1978.06.26 |
| 申请号 |
JP19760147443 |
申请日期 |
1976.12.07 |
| 申请人 |
MATSUSHITA ELECTRONICS CORP |
发明人 |
TAKAGI HIROMITSU;KANOU KOUTA |
| 分类号 |
G11C11/41;G11C11/40;H01L21/8244;H01L27/11;H01L27/12;H01L29/78 |
主分类号 |
G11C11/41 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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