发明名称 BUFFER MEMORY SWITCHING CIRCUIT
摘要 <p>PURPOSE:To read out plural buffer memories in use in a determined sequence by providing a buffer memory switching means switching a succeeding buffer memory according to the predetermined sequence when a prescribed pattern data read from a buffer memory is detected. CONSTITUTION:When an input frame data is subjected to coding processing by coding sections 41-4n, the processed data is sent to pattern generating means 61-6n whose processing end flag is corresponded when the coding processing is finished. The pattern generating means 61 writes the processing data when it is inputted and the prescribed pattern data when an end flag is written to the same area of a corresponding buffer memory 71. The processing data and the prescribed pattern data are read from the buffer memory 71, and when the prescribed pattern data is detected by a buffer memory switching section 8, the succeeding buffer memory is switched according to the predetermined sequence. Thus, when plural buffer memories are in use, the memories are read in the predetermined sequence.</p>
申请公布号 JPH02244886(A) 申请公布日期 1990.09.28
申请号 JP19890064233 申请日期 1989.03.16
申请人 FUJITSU LTD 发明人 HIGUCHI TAKEHIKO
分类号 H04N19/00;G06T1/60;H04N19/423;H04N19/436;H04N19/46;H04N19/50;H04N19/70;H04N19/93 主分类号 H04N19/00
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