发明名称 MEMORY INTEGRATED CIRCUIT
摘要 PURPOSE:In pre-charge, etc. , the 1st and 2nd digit lines are made to balance forcibly by a coupling transistor, thereby shortening the access time and cycle time in the starting of the read.
申请公布号 JPS5354430(A) 申请公布日期 1978.05.17
申请号 JP19760129909 申请日期 1976.10.27
申请人 NIPPON ELECTRIC CO 发明人 WADA TOSHIO
分类号 G11C11/409;G11C11/4091 主分类号 G11C11/409
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