发明名称 |
Process for preparing complementary MOS integrated circuit |
摘要 |
A process for preparing a complementary MOS integrated circuit by forming a shallow first source-drain region near the gate; determining simultaneously the contact holes in the source-drain regions of both of the P-channel and N-channel transistors; forming a deep second source-drain region from the contact holes using thermal diffusion; and forming the electrodes at the contact holes.
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申请公布号 |
US4084311(A) |
申请公布日期 |
1978.04.18 |
申请号 |
US19760732859 |
申请日期 |
1976.10.15 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
YASUOKA, AKIHIKO;SHIBATA, HIROSHI |
分类号 |
H01L21/8238;H01L27/092;H01L29/78;(IPC1-7):B01J17/00 |
主分类号 |
H01L21/8238 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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