发明名称 MULTIPLICATION CIRCUIT CONTAINING FIELDDEFFECT TRANSISTOR
摘要 PURPOSE:To secure an equal slope for the property curves of the drain current against each binary signal input voltage by inserting resistance into the drain input circuit of FET and adjusting the resistivity, and thus to delete the difference between the both properties as well as to enlage the linearity range.
申请公布号 JPS5338945(A) 申请公布日期 1978.04.10
申请号 JP19760113041 申请日期 1976.09.22
申请人 HITACHI LTD 发明人 MIYAGAWA NOBUAKI;MIKI MASAYUKI
分类号 G06G7/163;G06G7/16 主分类号 G06G7/163
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