| 摘要 |
An arithmetic logic unit employing soft-saturating current mode logic gates receives as inputs two 4-bit plus parity bytes and generates a 4-bit plus parity binary output byte in accordance with the particular operational mode prescribed by a binary operation mode control signal. The unit performs sixteen binary arithmetic or sixteen Boolean logic operations on two 4-bit plus parity input fields Ai and Bi. A carry-in input CIN, a carry generate output G, and a carry propogate output P are provided so that the device can be utilized in a full carry look-ahead configuration with a separate carry look-ahead array. A special output F=O is provided for zero detection purposes. In addition to the arithmetic and logic operations, the unit performs parity checking, parity carry, and parity prediction operations on the 4-bit plus parity binary input signals, and accordingly special inputs in the form of a carry-in duplicate CID, parity of the half-sums HS, a parity of the half-parities HP, parity of the carries PC, carry error CE, and parity checking command PCK are provided. A special output E indicates a carry or half-sum parity error. A carry-out signal COUT is also provided. The device can be configured to operate on bytes having fewer than four data bits by means of a pair of configuration select signals P1 and P2.
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