发明名称 SIGNAL DELAY CIRCUIT AND CLOCK SIGNAL GENERATION CIRCUIT USING THE SAME
摘要 PURPOSE:To evade influence by dispersion in a specification source voltage, an ambient temperature, or a manufacturing condition, etc., applying control by a phase locked loop consisting of a charge pump circuit, a delay means, and a logic circuit. CONSTITUTION:A signal delay circuit is comprised of a reference current setting circuit 1, the charge pump circuit 2, a low-pass filter circuit 3, a delay circuit 4, and the logic circuit 5. The reference current setting circuit 1 sets respective reference current value for a current that flows in to and flows out from a capacitor at the charge pump circuit 2. When coincidence between the current capacity ratio of transistors 27 and 30 coincides with the inverse of a ratio of an input clock signal CLKIN to the pulse width of the output signal (c) of the logic circuit 5, an electric charge quantity flowing in the capacitor 31 becomes equal to the quantity flowing out from the capacitor, and the voltage value of an output signal (d) from the low-pass filter circuit 3 can be stabilized at an arbitrary value. At such a time, a delay quantity at each delay stage in the delay circuit 4 to which a constant voltage is supplied can be kept constant.
申请公布号 JPH02276311(A) 申请公布日期 1990.11.13
申请号 JP19890331131 申请日期 1989.12.22
申请人 TOSHIBA CORP;TOSHIBA MICRO ELECTRON KK 发明人 OSANAGA AKIRA;MATSUO KENJI;MOGI HIROYUKI;UCHIDA HIDEAKI
分类号 H03K5/135;G11C11/4076;H03K5/00;H03K5/133;H03K5/134;H03K19/003;H03L7/00 主分类号 H03K5/135
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