| 摘要 |
A data compression apparatus is described having an encoder and a decoder. Data in the form of an N-bit data message from an external data source is received in the encoder and stored in an N-bit memory. Coupled to the memory is a "one's" detector and three arithmetic units. The "one's" detector counts the number of logical "one's" in the N-bit message irrespective of their position in the memory for generating a number Q. The three arithmetic units sum columns of the contents of the memory in three predetermined sequences for generating three numbers A, B and C. The numbers A, B, C and Q are then used to form a P-bit data message, where P is less than N for a sufficiently large N - e.g., for N=256, N/P is approximately 2.8 - for transmission to the decoder. The decoder is provided with an N-bit memory, three arithmetic units and a comparison circuit. Upon receipt of the P-bit data message, Q logical "one's" are stored in the decoder memory. The arithmetic units in the decoder, as in the encoder, sum columns of the contents of the decoder memory in three sequences for generating three numbers A', B' and C'. The numbers A', B', and C' are compared with the numbers A, B and C in the comparison circuit. A shifting circuit controlled by the comparison circuit repetitively shifts the logical "one's" in the decoder memory until A'=A, B'=B and C'=C. When A'=A, B'=B and C'=C, the original N-bit data message is recreated and is available for use by an external utilization apparatus.
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