发明名称 DATA CONTROL SYSTEM
摘要 PURPOSE:To considerably reduce a data transfer time and to effectively use a buffer memory of small capacity by starting a transfer to a data pool memory in parallel with the start of the input of a data frame and completing the transfer to the data pool memory when a completion recognizing bit detects, for instance, '1' state. CONSTITUTION:A completion recognizing bit area is added to the data frame, when the input start of the data frame is detected by a data receiving part 10, a control processor 3 simultaneously instructs a transfer control to the data pool memory 4 to a data transfer control part 30 by the interruption signal and starts the transfer. At this time, when the data transfer control part 30 detects that the completion recognizing bit added in the data receiving part 10 is brought into, for instance, '1' state, it completes the transfer to the data pool memory 4. Thereby, the data transfer time can be considerably reduced and the buffer memory 20 of the small capacity can be effectively utilized.
申请公布号 JPS62263555(A) 申请公布日期 1987.11.16
申请号 JP19860106481 申请日期 1986.05.09
申请人 PFU LTD 发明人 KURITA HITOSHI
分类号 G06F13/00;G06F13/38 主分类号 G06F13/00
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