发明名称 |
Full adder/subtractor circuit employing exclusive OR logic |
摘要 |
A binary full adder/subtractor circuit includes an exclusive OR gate operating upon augend/minuend and addend/subtrahend binary input signals. The sum/difference output from the circuit is the carry/borrow input signal or its inverse depending upon the output state of the exclusive OR gate. The carry/borrow output of the circuit comprises either the carry/borrow input or the addend/subtrahend input, as determined by the output of the exclusive OR gate and by an operation (sum/difference) specifying input signal.
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申请公布号 |
US4071905(A) |
申请公布日期 |
1978.01.31 |
申请号 |
US19760736236 |
申请日期 |
1976.10.27 |
申请人 |
NIPPON ELECTRIC CO., LTD. |
发明人 |
OGUCHI, TETSUJI;KAWAI, HIROKAZU |
分类号 |
G06F7/501;G06F7/50;G06F7/503;G06F7/506;(IPC1-7):G06F7/50 |
主分类号 |
G06F7/501 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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