Multistage frequency pulse divider - has shift register with NAND: gate feeding stage outputs back to input

摘要

The pulse frequency divider has an n-stage shift register with feedback. The outputs of k >=2 stages (FF1, FF2) of the register are connected to the k inputs of a NAND-gate (T3) whose output is coupled back to the input of the registers first stage. The registers first to (n-k) stages have no feedback. The divided pulse sequence is taken from the output (A) of one stage (FF2). In another version inverters are located between the outputs of the second and nth stages and the inputs of the NAND-gate. A further NAND-gate is connected in series after each inverter. This second version allows pulse trains with variable duty factor and frequency to be generated.