发明名称 |
Digital phase-locked loop filter |
摘要 |
A phase processing system which includes at least one digital phase-locked loop wherein the phase of the input signal to the loop is compared with the phase of the loop output signal to produce a pulse-width modulated phase error signal. The error signal is digitally integrated, as by a counting means which cyclically counts the pulse widths thereof and provides a first control signal when the count reaches a first value and a second control signal when the count reaches a second value. The control signals are used to control the pulse rate of a clock signal to produce an intermediate clock signal such that when the first control signal is present a pulse is added thereto and when the second control signal is present a pulse is deleted therefrom. The intermediate clock signal is then fed to a feedback divider counting means which provides the loop output signal.
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申请公布号 |
US4066978(A) |
申请公布日期 |
1978.01.03 |
申请号 |
US19770761853 |
申请日期 |
1977.01.24 |
申请人 |
THE CHARLES STARK DRAPER LABORATORY, INC. |
发明人 |
COX, JR., DUNCAN B.;LEE, WILLIAM H. |
分类号 |
H03H17/02;H03L7/07;H03L7/099;H04L7/033;(IPC1-7):H03B3/04 |
主分类号 |
H03H17/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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