| 摘要 |
The present invention achieves technical advantages as an in-band FEC syndrome generator and computation circuit. Three syndrome generators are utilized to generate 3 syndromes comprising polynomials. Each syndrome generator is comprised of two linear feedback shift registers (LFSR). Each LFSR operates in both 4-bit parallel mode and a 1-bit serial 39 bit mode. The two LFSRs work together to allow data to continuously be shifted in and the syndrome be generated. The first LFSR shifts in information bits, and at the end of each message, after the information bits have been shifted in, the first LFSR dumps its contents into the second LFSR. This second LFSR shifts in the 39 checkbits which performs the modulus operation. The contents of the second LFSR contain the syndrome once the checkbits have been shifted in. Then, these checkbits are shifted out, 4 bits at a time.
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