发明名称 RELOADABLE CAPACITIVE MEMORY ARRAY
摘要 A novel memory array is disclosed, the array utilizing a matrix of variable threshold insulated gate field effect transistor cells. The cells are comprised solely of a gate region, having nitride and oxide layers, and a source region with the output data sensed, at the source, as a change of source charge as distinguished from the prior art sensing of a change of low impedance source voltage. In operation, each cell functions as an alterable capacitor. A negative pulse applied to the gate selects the cell. Variations in stored charge at the nitride-oxide interface causes changes in the threshold voltage and effective capacitance of the cell. The source charge may then be sensed to read the stored data.
申请公布号 JPS52155930(A) 申请公布日期 1977.12.24
申请号 JP19770068045 申请日期 1977.06.10
申请人 NCR CO 发明人 JIYOOJI KOOBIN ROTSUKUUTSUDO;NIKORASU EDOWAADO ANESHIYANSUR
分类号 G11C17/04;G11C11/24;G11C11/403;G11C14/00;G11C16/04;H01L21/8246;H01L27/112;H01L29/78 主分类号 G11C17/04
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