Weight multiplier for use in an adapter processor

摘要

A weight multiplier for use in an adaptive processor. The input signal from a tapped delay line is split in a 3 dB hybrid into two equal level and equal phase signals. Each signal is fed to a mixer together with a signal performing the function of an oscillator signal. Output signals from the mixer are subtracted in a broadband hybrid. The result of this subtractor is then fed to a summer to supply a loop feedback signal.