| 摘要 |
There is disclosed a shift register circuit including plural stages of signal holding circuits (FF' n) which are cascade-connected to hold a signal based on a supplied input signal, to output an output signal (out) based on the held signal based on the supplied input signal, and to supply the output signal as an input signal to a subsequent stage, each of the plural stages of signal holding circuits including an output circuit which is supplied with two types of clock signals consisting of a first clock signal (ck) and a second clock signal (ck'), a timing of the second clock signal is delayed by a predetermined delay time with respect to a timing of applying the input signal (IN), which is supplied with a signal at a timing delayed by the delay time of the second clock signal from the timing of applying the input signal, and which outputs the output signal (OUT) at a timing responsive to the first clock signal. Also disclosed is a display drive device including the shift register circuit. ® KIPO & WIPO 2008
|
