| 摘要 |
A delay locked loop is provided to reduce a current consumption by variously optimizing a current quantity necessary for an operation based on a combination signal of a delay start signal and a test mode setting signal. A delay locked loop includes a delay chain(200), a delay cell current amplifying unit(300), and a bias unit(10). The delay chain has a plurality of delay cells which are coupled in series, and receives a couple of external clock signals. The delay chain selects a predetermined number of delay cells to perform an output operation in response to a plurality of output sell selection signals. The delay chain outputs a couple of delayed clock signals and a couple of phase combination clock signals. The delay cell amplifying unit receives a couple of last delayed clock signals of the couple of delayed clock signals. If a duty ratio of a couple of last delayed clock signals is distorted in response to a combination of a test mode setting signal and a delay start signal of a bit of a plurality of delay operation start signals, the delay cell amplifying unit corrects and amplifies uniformly the duty ratio by adjusting a reference phase voltage. The bias unit supplies independently first and second bias currents necessary for an operation of the delay chain and the delay cell current amplifying unit. |
