| 摘要 |
An oscillator circuit comprised of three bistable circuits connected in cascade, a circuit for generating first timing signals, and a circuit for generating second timing signals. Output signals from the series of bistable circuits are applied to enable the circuits for generating timing signals, and the timing signals are applied to an input of the series of bistable circuits to change the states of the bistable circuits. After a first time interval has elapsed the first timing signal changes the state of a first bistable circuit which in turn successively changes the states of the other bistable circuits. After a second time interval has elapsed after the changes of state effectuated by the first timing signal, the second timing signal changes the state of the first bistable circuit which in turn successively changes the states of the other bistable circuits, so that the bistable circuits repetitively change state with a period equal to the sum of the first and the second time intervals.
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