摘要 |
<p>A universal timing circuit is designed to provide a variety of operational modes: monostable operation may generate a pulse output of shorter duration than the input. The circuit may generate an output pulse of fixed duration independent of multi cycle switching of the input. An output delay may be triggered off the trailing edge of the input. There is a clock generator mode and a pulse stretcher. The circuit consists of a gated oscillator formed by NAND gates (2, 3) operating into a frequency counter (4) with R-C feedback elements (R1, R2, C1). A reset circuit is provided by a NOR gate(5), delay (8), EXCLUSIVE-OR (6) and reset memory (9).</p> |