| 摘要 |
A symmetric, two-branched transistor switching circuit is disclosed wherein steering current is fed to a node between the two branches. A logic input signal controls the electrical balance between the two branches controlling the flow of steering current from one branch to the other and back, depending upon two discrete logic input levels. The two-branched circuit is connected to a pair of loads, one associated with each circuit branch as well as to a common node which may be connected to an auxiliary circuit. By a balanced circuit configuration and supplying properly regulated bias during a logic input transition, the effects of parasitic capacitance, which normally delays switching times, may be reduced, thereby permitting the switching of very low levels of current, i.e. on the order of 1 or 2 microamperes at speeds comparable to those obtained when switching 1 or 2 ma. An auxiliary circuit which may be connected to the common node of the circuit is an electrical ladder which decrements current. A balanced output is provided in a pair of output lines for supplying an output current IOUT and its complement IOUT.
|
