| 摘要 |
<p>1407163 Digital transmission; coding GENERAL MOTORS CORP 18 Jan 1973 [28 Jan 1972] 2581/73 Heading H4P A coding method comprises sensing each bit and generating an output stream which if a pair of like adjacent bits is sensed produces a first transistion at a first time if the sensed pair is 11 or a second time if sensed pair is 00. The state of the next bit is inverted if a next same bit follows a pair of like bits. If an alternate pattern follows of at least 7 bits, a second transition is produced as output at 2 or 2¢ bit periods dependent on the commencing bit and a series of third transitions every 1¢ bit times is produced after the second transition until a minimum of two bit times prior to detecting a further pair of adjacent bits of the same type following the alternate pattern. The arrangement provides not more than one transition each 1¢ bit time and is never at one level for more than f bit times hence stabilizing D.C. level in an output bit stream. The coder has a 9 bit input register 12 receiving NRZL data. A bit in position 8 is compared with position 9 by comparator 14 which triggers an output state controller 16 at the beginning of bit time if 8, 9 are 1's, and middle of bit time if 0's thereby introducing a state change. Comparator 14 also enables seven bit alternate pattern detector 18 and pulse generator 20 which produces 1¢ bit interval pulses. Detector 18 senses level of bits 1-7 in register 12 and produces a START output to pulse generator 20 when 8, 9 are like and 1-7 alternate. If alternate pattern commences 10 (01), pulse generator 20 is enabled ¢ (1) bit thereafter and causes 16 to produce a first state change 2 (2¢) bit times later; means 20 then issues a series of pulses at 1¢ bit times until disabled by 3 bit non-alternate detector 22 responsive to bits 5-7 in register 12. When 5, 6 are at the same level i.e. STOP signal is fed to generator 20. Output of compator 14 is also fed back to register 12 which switches level of bit 8 following detection of a pair of like bits in sections 7, 8 so that only discrete pairs of 0's or 1's are detected and shifting of 000's or 111's through positions 8, 9 is not interpreted as 00's or 11's. Other Figures showing logic diagrams are described in detail, together with a decoder illustrated in block form in Fig. 5 (not shown).</p> |
