发明名称 Low power dissipation combined enhancement depletion switching driver circuit
摘要 In a push-pull output circuit comprising inverters, each using a depletion-type load field-effect transistor (FET) and an enhancement-type driving FET, an intermediate inverter including a depletion-type load FET and an enhancement-type driving FET is added between the input side and output side inverters. The load impedance of the output side inverter is set at a value much smaller than those of the other inverters. The utilization of a power supply voltage is enhanced because of the use of depletion-type FET's and the total current in the circuit is low due to the use of the intermediate inverter.
申请公布号 US4042839(A) 申请公布日期 1977.08.16
申请号 US19760660777 申请日期 1976.02.24
申请人 HITACHI, LTD. 发明人 ARAKI, YOSHIKAZU
分类号 H03K5/02;H03K19/0185;H03K19/0944;(IPC1-7):H03K19/08;H03K19/40;H03K17/04;H03K17/10 主分类号 H03K5/02
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