In-between phase clamping circuit to reduce the effects of positive noise

摘要

An improved MOS clamping circuit compatible with a multi-phase, major-minor clocking scheme. The present circuit is adapted to clamp the output terminal of a conventional major logic gate to a negative signal level. The instant clamping circuit prevents the deterioration of the logic gate output signal as a consequence of positive noise during the minor clock phases and during an in-between clock phase, which phase corresponds to the interval of time between the occurrence of first and second major clock phases.