发明名称 MEMORY CIRCUIT
摘要 PURPOSE:To reduce the power consumption of the logic input section at the hold condition, by improving the logic input section controlling the memory cell of PNPN constitution of which off hold current is zero, and by forming the logic input section thru the use of each two of PNP and NPN transistors.
申请公布号 JPS5292443(A) 申请公布日期 1977.08.03
申请号 JP19760008466 申请日期 1976.01.30
申请人 HITACHI LTD 发明人 OOHINATA ICHIROU
分类号 G11C11/41;G11C11/411 主分类号 G11C11/41
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