| 摘要 |
Decoding apparatus for separating clock and data pulses from a double-frequency pulse train, including a retriggerable window one-shot, a bit shift compensation circuit, clock rate tracking means, data bit and clock bit gates, means for keeping track of whether a specific pulse is a data pulse or a clock pulse, and means for actuating the data bit and clock bit gates, based on the status of the system and the state of the window one-shot. The apparatus also provides means for detecting when a clock pulse is missing, including circuitry which simulates the detection of a clock pulse to the rest of the device to keep the system status and timing properly synchronized to the pulse train data.
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