| 摘要 |
<p>1291621 Capacitor chain signal delay networks INTERNATIONAL STANDARD ELECTRIC CORP 14 July 1970 [24 July 1969] 34043/70 Heading H3U An analogue signal delay device comprises a number n of delay circuits in parallel, each operated at a frequency greater than In times the highest frequency to be passed by the device and each delay circuit being of the type in which the signal is passed along a succession of storage elements. As shown, the delay circuits are formed by capacitors coupled by the emitter-base path of a transistor and the control signal to the common connection of the base and the capacitor being in opposite phase in alternate stages and, when there are two parallel circuits, in opposite phase in the two circuits. The parallel circuits may be succeeded and preceded by single delay chains and the control signal for the parallel paths obtained from the control signal for the single chains via a frequency divider. The control signals may be fed only to the capacitors, Fig. 4, not shown. The parallel circuits may be fed from a common sampler or respective samplers. The control signal component in the output may be cancelled by using control signals of opposite phase or by temporarily connecting an additional capacitor across the output capacitor.</p> |
