发明名称 |
PERFECCIONAMIENTOS EN MULTIPLICADORES SERIALES DIGITALES. |
摘要 |
<p>The present invention includes a substantially modular pipeline multiplier for directly forming the correct final product of a 2's complement data word and a sign and magnitude coefficient word. In particular, the present invention includes circuitry for inserting logic 1 signals into the computations as sign extensions during multiplication whenever the data word is a negative 2's complement number.</p> |
申请公布号 |
ES443696(A1) |
申请公布日期 |
1977.05.01 |
申请号 |
ES19960004436 |
申请日期 |
1975.12.19 |
申请人 |
WESTERN ELECTRIC COMPANY, INCORPORATED |
发明人 |
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分类号 |
G06F7/533;G06F7/508;G06F7/52;G06F7/525;(IPC1-7):06F/ |
主分类号 |
G06F7/533 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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