发明名称 FIELD EFFECT SEMICONDUCTOR ARRANGEMENT
摘要 <p>1471282 IGFET's INTERNATIONAL BUSINESS MACHINES CORP 25 June 1974 [28 July 1973] 28022/74 Heading H1K In an IGFET, which includes a source and a drain defining a channel therebetween, the length L of the channel, Fig. 4A, being the distance between the source and drain, and a gate electrode which overlies the channel and a region of the semi-conductor substrate alongside the channel, the width W of the channel, Fig. 4B, is made sufficiently small such that, in operation, it has a direct influence on the value of the threshold voltage of the transistor-a reduction in the channel width W producing an increase in the threshold voltage VT, as shown in Fig. 3B, in which d 2 /d 1 is the ratio of, respectively, the depletion layer depth in the region alongside the channel to that in the channel. Utilizing this effect with the known effect that a reduction in the channel length decreases the threshold voltage, then a device of much smaller channel area can be produced while maintaining a desired threshold voltage level. In addition field effect transistors can be formed having different threshold voltage values in the same semi-conductor substrate without needing any additional processing steps merely by choosing different channel widths for the devices. Although in the present arrangement the channel width W is fixed by the choice of threshold voltage and other design criteria determine the optimum channel length L, the impedance value of the FET which depends on the channel width to channel length ratio W/L can be varied by the arrangement shown in Figs. 4A and 4B. In this arrangement a number of FET's of narrow channel width W have common source and drain zones 24, 34, with the gate zones of length L and width W formed by thin zones 54 of insulating layer 44. A common gate electrode 64 is provided and the resulting overall transistor has a threshold voltage which is determined by the channel width W of an individual part-transistor and an impedance value which is determined by the effective resulting channel width W R which is equal to the sum of the individual channel widths W. The width of the channel may be defined by doped zones in the substrate on either side of the channel.</p>
申请公布号 CA1005930(A) 申请公布日期 1977.02.22
申请号 CA19740203550 申请日期 1974.06.27
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 BAITINGER, UTZ G.;FOLBERTH, OTTO G.;HAUG, WERNER;KROELL, KARL-EUGEN
分类号 H01L21/8234;H01L21/331;H01L27/06;H01L27/088;H01L29/00;H01L29/10;H01L29/423;H01L29/73;H01L29/78 主分类号 H01L21/8234
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