| 摘要 |
PURPOSE: A TFT(thin film transistor) fabrication method is provided to minimize contact resistance by etching an amorphous silicon layer using a protecting layer as a mask. CONSTITUTION: A gate electrode(21), a gate insulating layer(30), an amorphous silicon layer (40), and two heavily doped amorphous silicon parts(51,52) are sequentially formed on a substrate(10). A source electrode(61) and a drain electrode(62) are formed on the heavily doped amorphous silicon parts(51,52). A first protecting layer(70) is stacked on entire surface of the resultant structure. The heavily doped amorphous silicon parts(51,52) between the source electrode(61) and the drain electrode(62) are exposed by etching the first protecting layer(70). The amorphous silicon layer(40) is exposed by etching the heavily doped amorphous silicon parts(51,52).
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