| 摘要 |
A circuit comprises a phase combiner and four output ports. The phase combiner adds an in-phase positive input and a quadrature positive input to obtain an in-phase positive output, adds an in-phase negative input and a quadrature negative input to obtain an in-phase negative output, adds the in-phase negative input and the quadrature positive input to obtain a quadrature positive output, and adds the in-phase positive input and the quadrature negative input to obtain a quadrature negative output. The four output ports, are respectively configured to output the in-phase positive output, the in-phase negative output, the quadrature positive output, and the quadrature negative output. |
| 主权项 |
1. A circuit, comprising:
a phase combiner, configured to:
add an in-phase positive input and a quadrature positive input to obtain an in-phase positive output;add an in-phase negative input and a quadrature negative input to obtain an in-phase negative output;add the in-phase negative input and the quadrature positive input to obtain a quadrature positive output;add the in-phase positive input and the quadrature negative input to obtain a quadrature negative output; four output ports, respectively configured to output the in-phase positive output, the in-phase negative output, the quadrature positive output, and the quadrature negative output; a first power detector, configured to convert the in-phase positive output and the in-phase negative output to a first direct voltage; a second power detector, configured to convert the quadrature positive output and the quadrature negative output to a second direct voltage; and a comparator, configured to compare the first direct voltage and the second direct voltage, and feed comparison result back to the phase combiner;wherein
the phase combiner further comprises a first NMOS, a second NMOS, a third NMOS, a fourth NMOS, a fifth NMOS, a sixth NMOS, a seventh NMOS and an eighth NMOS, a first impedance, a second impedance, a third impedance and a fourth impedance, wherein a gate of the first NMOS is configured to receive the in-phase positive input, a gate of the second NMOS receives the in-phase negative input, a gate of the third NMOS is configured to receive the quadrature positive input, a gate of the fourth NMOS is configured to receive the quadrature negative input, drains of both the first NMOS and third NMOS are connected to the first impedance, and the first impedance is connected to Vcc, drains of both the second NMOS and the fourth NMOS are connected to the second impedance, and the second impedance is connected to Vcc; and a gate of the fifth NMOS is configured to receive the quadrature positive input, a gate of the sixth NMOS is configured to receive the quadrature negative input, a gate of the seventh NMOS is configured to receive the in-phase negative input, a gate of the eighth NMOS is configured to receive the in-phase positive input, drains of both the fifth NMOS and seventh NMOS are connected to the third impedance, and the third impedance is connected to Vcc, drains of both the sixth NMOS and the eighth NMOS are connected to the fourth impedance, and the fourth impedance is connected to Vcc. |
