发明名称 |
DMA data path aligner and network adaptor utilizing same |
摘要 |
A data path aligner transfers data from an input having N byte lanes with byte enable bits to an output having N byte lanes. The aligner includes first stage having N-1 selector/registers, and a second stage having N selector/registers. Each of the N-1 selector/registers S1(i) in the first stage has inputs including input lanes L(j) for j going from i+1 to N. Each of the selector/registers S2(i) in the second stage has inputs including input lanes L(k) for k going from i to 0, and for selector/registers S2(i) for i less than or equal to N-2, the inputs include the output of a first stage selector/register S1(i). The outputs of the second stage selector/registers supply data selected from the respective inputs to output segment lanes. All of these selector/registers are controlled by a common select signal derived from a data path offset, and all selector/registers are clocked by a common clock.
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申请公布号 |
US5392406(A) |
申请公布日期 |
1995.02.21 |
申请号 |
US19920947055 |
申请日期 |
1992.09.18 |
申请人 |
3COM CORPORATION |
发明人 |
PETERSEN, BRIAN;LO, LAI-CHIN;BROWN, DAVID R. |
分类号 |
G06F5/00;G06F13/28;G06F13/40;(IPC1-7):G06F13/00 |
主分类号 |
G06F5/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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