发明名称 GRAIN BOUNDARY BLOCKING FOR STRESS MIGRATION AND ELECTROMIGRATION IMPROVEMENT IN CU INTERCONNECTS
摘要 <p>GRAIN BOUNDARY BLOCKING FOR STRESS MIGRATION AND ELECTROMIGRATION IMPROVEMENT IN C U INTERCONNECTS Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted alloying elements that block grain boundaries and reduce stress and electro migration. In a first example embodiment, the barrier layer is left over the inter metal dielectric layer during the alloying element implant. The barrier layer is later removed with a planarization process. In a second example embodiment the barrier layer is removed before the alloying element implant and a hard mask blocks the alloying element from being implanted in the inter metal dielectric layer. Figure IE</p>
申请公布号 SG149010(A1) 申请公布日期 2009.01.29
申请号 SG20080091456 申请日期 2006.04.24
申请人 CHARTERED SEMICONDUCTOR MANUFACTURING LTD 发明人 FAN ZHANG;LIEP CHOK KHO;SEE ALEX;CHEH TAN CHENG;XIAOMEI BU;JONG LEE TAE;CHOO HSIA LIANG
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