发明名称 BIT SYNCHRONIZATION DETECTION SYSTEM
摘要 <p>PURPOSE:To sufficiently correspond to data even with a short packet length by operating a bit synchronization detecting circuit in accordance with a first mode in a period when a prescribed pattern is detected and operating a bit synchronization detection means in accordance with a second mode in a period when the prescribed signal pattern is not detected. CONSTITUTION:A signal processing circuit 2 identifies the data of a reception base band signal RD fitted to bit pull-in and a preamble bit is arranged for the leading part of packet data. In such a case, the bit synchronization control means operates the bit synchronization detecting circuit 4 in accordance with the first mode in the period when the specified signal pattern is detected in the signal pattern detection means and operates the bit synchronization detecting means in accordance with the second mode in the period when the specified signal pattern is not detected. Thus, correspondence to data with the short packet length can sufficiently be executed and reception data can stably be reproduced.</p>
申请公布号 JPH0418829(A) 申请公布日期 1992.01.23
申请号 JP19900115490 申请日期 1990.05.01
申请人 TOSHIBA CORP;TOSHIBA AVE CORP 发明人 GOTO TADAMASA;KOIKE SHUNSUKE
分类号 H04J3/06;H04L7/04 主分类号 H04J3/06
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