ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT

摘要

A method of forming a dual damascene metal interconnect for a semiconductor device. The method includes forming a layer of low-k dielectric, forming vias through the low-k dielectric layer, depositing a sacrificial layer, forming trenches through the sacrificial layer, filling the vias and trenches with metal, removing the sacrificial layer, then depositing an extremely low-k dielectric layer to fill between the trenches. The method allows the formation of an extremely low-k dielectric layer for the second level of the dual damascene structure while avoiding damage to that layer by such processes as trench etching and trench metal deposition. The method has the additional advantage of avoiding an etch stop layer between the via level dielectric and the trench level dielectric.

主权项

1. A semiconductor device manufacturing process, comprising:
providing a substrate; forming a first dielectric layer over the substrate; patterning a via opening in the first dielectric layer; forming a sacrificial layer over the first dielectric layer; patterning a trench opening through the sacrificial layer; filling the via opening and trench opening with conductive material; removing the sacrificial layer; and forming a second dielectric layer over the first dielectric layer, wherein the second dielectric layer has a lower dielectric constant than the first dielectric layer.