发明名称 THREE DIMENSIONAL RESISTIVE MEMORY ARCHITECTURES
摘要 In one example, a three dimensional resistive memory architecture includes adjacent memory tiles with each tile including a multilevel resistive crossbar. array and at least one decoder. The multilevel crossbar array includes layers of row crossbars, layers of column crossbars, and layers of resistive memory elements interposed between cross points of the row crossbars and the column crossbars, in which at least one layer of crossbars extends from a first tile through an adjacent tile and is used to address resistive memory elements in the adjacent tile. The at least one decoder underlies the multilevel resistive crossbar array and includes an address matrix comprising digital lines and analog lines, in which the digital lines select which crossbars are connected to the analog lines.
申请公布号 US2016247565(A1) 申请公布日期 2016.08.25
申请号 US201315031813 申请日期 2013.10.31
申请人 HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP 发明人 Perner Frederick;Rho Kwangmyoung;Kim Jeong Hwan;Hwang Sangmin;Park Jinwon;Yi Jae Yun;Lee Jae Yeon;Chung Sung Won
分类号 G11C13/00;H01L27/24 主分类号 G11C13/00
代理机构 代理人
主权项 1. A three dimensional resistive memory architecture comprising: adjacent memory tiles, each tile comprising: a multilevel resistive crossbar array comprising layers of row crossbars, layers of column crossbars, and layers of resistive memory elements interposed between cross points of the row crossbars and the column crossbars, in which at least one layer of crossbars extends from a first tile through an adjacent the and is used to address resistive memory elements in the adjacent tile;at least one decoder underlying the multilevel resistive crossbar array comprising an address matrix comprising digital lines and analog lines, in which the digital lines select which crossbars are connected to the analog lines.
地址 Houston TX US