发明名称 |
NORMALIZING CIRCUIT OF BINARY-CODED DECIMAL NUMBER |
摘要 |
PURPOSE:To attain a high-speed operation of a normalizing circuit of binary- coded decimal number by shifting the input data after detecting ''1'' that is most approximate to the most significant bit of the input data. CONSTITUTION:A preceding ''1'' detecting circuit 1 uses the data X of mantissa part as an input and detects ''1'' most approximate to the most significant bit MSB including this MSB and informs this detection information to an encoder 2. The encoder 2 converts the number of shifts into a code of binary display to perform normalization according to the received information. A shifter 3 obtains the input of the data X and shifts the data X according to the shift information which is coded by the encoder 2 to produce the nomalization data Y. This circuit ensures a normalizing action at a high speed. |
申请公布号 |
JPS6083139(A) |
申请公布日期 |
1985.05.11 |
申请号 |
JP19830191489 |
申请日期 |
1983.10.13 |
申请人 |
NIPPON DENKI KK |
发明人 |
KUWATA AKIRA;TAKAHASHI TOSHIYA |
分类号 |
G06F7/00;G06F5/01;G06F7/485;G06F7/494;G06F7/74 |
主分类号 |
G06F7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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