Decryption systems and related methods for on-the-fly decryption within integrated circuits

摘要

Methods and systems are disclosed for on-the-fly decryption within an integrated circuit that adds zero additional cycles of latency within the overall decryption system performance. A decryption system within a processing system integrated circuit generates an encrypted counter value using an address while encrypted code associated with an encrypted software image is being obtained from an external memory using the address. The decryption system then uses the encrypted counter value to decrypt the encrypted code and to output decrypted code that can be further processed. A secret key and an encryption engine can be used to generate the encrypted counter value, and an exclusive-OR logic block can process the encrypted counter value and the encrypted code to generate the decrypted code. By pre-generating the encrypted counter value, additional cycle latency is avoided. Other similar data independent encryption/decryption techniques can also be used such as output feedback encryption/decryption modes.

主权项

1. A method for an integrated circuit, comprising:
communicating between the integrated circuit and an external memory to obtain encrypted code associated with an encrypted software image stored in the external memory, the encrypted code being associated with an address; generating an encrypted counter value within the integrated circuit by encrypting a counter value at least in part while the encrypted code is being obtained, the counter value being based upon the address; after the encrypted code is obtained and after the encrypted counter value is generated, decrypting the encrypted code within the integrated circuit using the encrypted counter value to generate decrypted code associated with the encrypted software image; and communicating the decrypted code through a system bus interconnect for execution within the integrated circuit.